JEDEC Updates Standard for Low Power Memory Devices: LPDDR5

Faster, more efficient version offers new features targeting
automotive applications

Solid State Technology Association
, the global leader in standards
development for the microelectronics industry, today announced the
publication of JESD209-5,
Low Power Double Data Rate 5 (LPDDR5). LPDDR5 will eventually operate at
an I/O rate of 6400 MT/s, 50% higher than that of the first version of
LPDDR4, which will significantly boost memory speed and efficiency for a
variety of applications including mobile computing devices such as
smartphones, tablets, and ultra-thin notebooks. In addition, LPDDR5
offers new features designed for mission critical applications such as
automotive. Developed by JEDEC’s JC-42.6 Subcommittee for Low Power
Memories, LPDDR5 is available for download from the JEDEC

With the doubling of memory throughput over the previous version of the
standard (LPDDR5 is being published with a data rate of 6400 MT/s,
compared to 3200 MT/s for LPDDR4 at its publication in 2014), LPDDR5
promises to have an enormous impact on the performance and capabilities
of the next generation of portable electronic devices. To achieve this
performance improvement, LPDDR5 architecture was redesigned; moving to
16Banks programmable architecture and multi-clocking architecture.

LPDDR5 introduces two new command-based operations to improve system
power consumption by reducing data transmission: Data-Copy and Write-X.
The Data-Copy command instructs the LPDDR5 device to copy data
transmitted on a single I/O pin to the other I/O pins, eliminating the
need to transmit data to the other pins. The Write-X command instructs
the device to write all-ones or all-zeros to a specific address,
eliminating the need to send data from the SoC to the LPDDR5 device.
Reducing data transmission with these new commands will help reduce
overall system power consumption.

To address the need for data reliability in adjacent markets such as
automotive, LPDDR5 introduces the support of Link Error Correcting Code
(ECC) on the interface between the SoC and DRAM.

Key specification updates include:

  • I/O throughput up to 6400 Mbps

    • Signaling voltage – 250mV
    • Non-Target ODT for DQ was added to support higher data rate
    • Signal integrity enhancement by DFE
  • Clocking architecture: WCK & Read Strobe (RDQS) added to support
    higher data rate
  • Programmable Multi-bank organization (8Banks, 4Bank groups/4Banks, and
  • Selectable background and command based ZQ calibration
  • Low-power features added include

    • Dynamic Frequency and Voltage Scaling for Core and I/O
    • Selectable differential and single-ended CK, WCK, and RDQS
    • Partial array self-refresh and auto-refresh
    • Low power read/write operation with Data-Copy and Write-X functions
  • Function/Features targeting automotive applications including

    • Optional Link ECC
    • New packaging definition


JEDEC is the global leader in the development of standards for the
microelectronics industry. Thousands of volunteers representing nearly
300 member companies work together in over 100 JEDEC committees and task
groups to meet the needs of every segment of the industry, manufacturers
and consumers alike. The publications and standards generated by JEDEC
committees are accepted throughout the world. All JEDEC standards are
available for download from the JEDEC website. For more information,


Emily Desjardins

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